曹鹏

个人简介

amjs澳金沙门，副教授，博士生导师，任职于amjs澳金沙门国家ASIC工程中心（简称“国家ASIC中心”）和国家集成电路设计自动化技术创新中心（简称“EDA国创中心”），长期专注于宽电压电路时序分析和签核方法研究，近年来在IEEE TVLSI，IEEE TCAD, DAC, ICCAD, ASP-DAC，ISCAS等电路设计和EDA领域顶级期刊和会议发表论文30余篇，并获2021年和2022年 ASP-DAC会议最佳论文提名，担任IEEE TCAS-I, TCAS-II, TCAD, TVLSI等期刊审稿人，授权发明专利30余件，授权美国专利5件，作为负责人承担多项国家重点研发计划课题、国家自然科学基金课题及江苏省自然科学基金课题，依托东南大学与华大九天、国微、华为海思等国内顶尖EDA企业及设计公司成立的联合实验室，作为负责人承担多个EDA合作研发项目，并许可相关EDA企业使用本人作为第一发明人授权的发明专利应用于产品研发，获国家科技进步二等奖、中国专利金奖、江苏省科技进步一等奖，指导学生获得2023年集成电路EDA设计精英挑战赛最高奖菁英杯，并获得多项一等奖。

教育经历

1998.9-2002.6，东南大学无线电工程系，获工学学士学位；

2002.7-2010.3 东南大学电子科学与工程学院，硕博连读，获工学博士学位。

工作经历

2010.3-2015.7 东南大学电子科学与工程学院，讲师；

2015.7-2023.1 东南大学电子科学与工程学院，副教授；

2023.1-至今转至amjs澳金沙门。

讲授课程

承担本科生课程：计算机科学基础II，计算机综合课程设计。

获得东南大学第23届青年教师授课竞赛三等奖（2016年）。

教学研究

出版物

研究领域或方向

宽电压电路时序分析和签核方法、基于AI的EDA设计方法

研究项目

国家自然科学基金面上项目
国家重点研发计划课题光电子与微电子专项
江苏省自然科学基金面上项目

研究成果

发表论文：

Cheng Xu, Ye Yuyang, He Guoqing, Song Qianqian, and Cao Peng. Heterogeneous Graph Attention Network Based Statistical Timing Library Characterization with Parasitic RC Reduction[C]// 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 2024: 171–176.
He Guoqing, Ding Wenjie, Ye Yuyang, Cheng Xu, Song Qianqian, and Cao Peng. An Optimization-Aware Pre-Routing Timing Prediction Framework Based on Heterogeneous Graph Learning[C]// 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 2024: 177–182.
Cao Peng, Guoqing He, Wenjie Ding, Zhanhua Zhang, Kai Wang, and Jun Yang. Efficient and Accurate ECO Leakage Optimization Framework With GNN and Bidirectional LSTM[J], IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, 31(9): 1413–1424.
Cao Peng, He Guoqing, Yang Tai. TF-Predictor: Transformer-Based Prerouting Path Delay Prediction Framework[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023, 42(7): 2227–2237.
Cao Peng, Weixing Xu, Yuanjie Wu, Wanyu Liu, and Yu Wang: Subthreshold Delay Variation Model Considering Transitional Region for Input Slew[J]. Electronics, 2023, 12(3): 615.
Shen Shan, Cao Peng, Ling Ming, Shi Longxing. A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023, 42(4): 1223–1234.
Cao Peng, Yang Tai, Wang Kai, Bao Wei, Yan Hao. Topology-Aided Multicorner Timing Predictor for Wide Voltage Design[J]. IEEE Design & Test, 2023, 40(1): 62–69.
Cao Peng, and Jiahao Wang. Late Breaking Results: RL-LPO: Reinforcement Learning Based Leakage Power Optimization Framework with Graph Neural Network[C]// 2023 60th ACM/IEEE Design Automation Conference (DAC). 2023: 1–2.
Song, Qianqian, Cheng Xu, and Cao Peng. Critical Paths Prediction under Multiple Corners Based on BiLSTM Network[C]. 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023:1–6.
Jiang Haiyang, Cheng Xu, and Cao Peng. Multiple-Input Switching Modeling with Graph Neural Network[C]. 2023 International Symposium of Electronics Design Automation (ISEDA), 2023: 428–32.
Yang Tai, He Guoqing, Cao Peng. Pre-Routing Path Delay Estimation Based on Transformer and Residual Framework[C]//2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC). 2022: 184–189.（最佳论文提名）
Wang Kai, Cao Peng. A Graph Neural Network Method for Fast ECO Leakage Power Optimization[C]//2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC). 2022: 196–201.
Shen Shan, Cao Peng, Ling Ming, Shi Longxin. A Timing Yield Model for SRAM Cells in Sub/Near-threshold Voltages Based on A Compact Drain Current Model [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Accepted.
Guo Jingjing, Cao Peng, Li Mengxiao, Gong Yu, Liu Z, Bai G, Yang J. Semi-analytical Path Delay Variation Model with Adjacent Gates Decorrelation for Subthreshold Circuits[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021: 931–944.
Cao Peng, Bao Wei, Wang Kai, Yang Tai. A Timing Prediction Framework for Wide Voltage Design with Data Augmentation Strategy[C]// 26th Asia and South Pacific Design Automation Conference (ASP-DAC). 2021: 291–296.
Yan Hao, Shi Xiao, Xuan ChengZheng, Cao Peng, and Shi LongXing. An Adaptive Delay Model for Timing Yield Estimation under Wide-Voltage Range[C]// 26th Asia and South Pacific Design Automation Conference (ASP-DAC). 2021: 272-277.（最佳论文提名）
Jiang Haiyang, Xu Bingqian, Cao Peng, Cai Hao. Analytical Delay Model in Near-Threshold Domain Considering Transition Time[C]//2021 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA). 2021: 234–235.
Guo Jingjing, Cao Peng, Sun Zhaohao, Xu Bingqian, Liu Zhiyuan, Yang Jun. Novel Prediction Framework for Path Delay Variation Based on Learning Method[J]. Electronics, 2020, 9(1): 157.
Guo Jingjing, Cao Peng, Li Mengxiao, Liu Z, Yang J. Statistical Timing Model for Subthreshold Circuit with Correlated Variation Consideration[C]//2020 IEEE International Symposium on Circuits and Systems (ISCAS). 2020: 1–5.
Cao Peng, Bao Wei, Guo Jingjing. An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method[J]. Electronics, 2020, 9(4): 580.
Bao Wei, Cao Peng, Cai Hao, Bu Aiguo. A Learning-Based Timing Prediction Framework for Wide Supply Voltage Design[C]//Proceedings of the 2020 on Great Lakes Symposium on VLSI. 2020: 309–314.
Guo Jingjing, Cao Peng, Wu Jiangping, Liu Zhiyuan, Yang Jun. Analytical Gate Delay Variation Model with Temperature Effects in Near-Threshold Region Based on Log-Skew-Normal Distribution[J]. Electronics, 2019, 8(5): 501.
Cao Peng, Wu Jiangping, Liu Zhiyuan, Guo Jingjing, Yang Jun, Shi Longxing. A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region[C]//Proceedings of the 2019 on Great Lakes Symposium on VLSI. 2019: 323–326.
Cao Peng, Liu Zhiyuan, Xu Bingqian, Guo Jingjing. A Statistical Timing Model for CMOS Inverter in Near-threshold Region Considering Input Transition Time[C]//2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS). 2019: 586–589.
Cao Peng, Liu Zhiyuan, Wu Jiangping, Guo Jingjing, Yang Jun, Shi Longxing. A Statistical Timing Model for Low Voltage Design Considering Process Variation[C]//2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 2019: 1–8.
Cao Peng, Liu Zhiyuan, Guo Jingjing, Wu Jiangping. An Analytical Gate Delay Model in Near/Subthreshold Domain Considering Process Variation[J]. IEEE Access, 2019, 7: 171515–171524.
Cao Peng, Liu Zhiyuan, Guo Jingjing, Pang Haoyu, Wu Jiangping, Yang Jun. Accurate and Efficient Interdependent Timing Model for Flip-Flop in Wide Voltage Region[C]//2019 17th IEEE International New Circuits and Systems Conference (NEWCAS). 2019: 1–4.
Guo Jingjing, Cao Peng, Wu Jiangping, Xu Bingqian, Yang Jun. Path Delay Variation Prediction Model with Machine Learning[C]//2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). 2018: 1–3.
Cao P, Liu B, Yang J, Yang J, Zhang M, Shi L. Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 25(8): 2321–2331.

授权发明专利（均为第一发明人）

一种数字集成电路众工艺角延时预测方法（ZL202110582508.7）
一种近阈值单元电路延时模型（ZL202110631631.3）
一种寄存器时序约束灵活建模方法（ZL202110835923.9）
一种基于寄存器灵活时序库的电路时序优化方法（ZL202110906714.9）
先进工艺和低电压下的集成电路统计时序分析方法（ZL201910643441.6，许可国内EDA企业用于数字全流程EDA工具开发）
基于神经网络的单元延时预测方法和单元延时灵敏度计算方法（ZL201810940886.6，许可国内EDA企业用于数字全流程EDA工具开发）
一种抗功耗攻击的安全可重构架构（ZL201710373272.X）
一种基于寄存器掩码的面向AES算法的抗功耗攻击方法（ZL201610431897.2）
一种基于随机延时的面向AES算法的抗功耗攻击方法（ZL201610422789.9）
一种基于随机延时的面向DES算法的抗功耗攻击方法（ZL201610422786.5）
一种基于寄存器掩码的面向DES算法的抗功耗攻击方法（ZL201610412868.1）
一种可重构系统的动态局部重构控制器及其控制方法（ZL201510890096.8）
一种基于大规模粗粒度可重构处理器的SHA256实现方法及系统（ZL201510886219.0）
可重构系统和可重构阵列结构及其应用（ZL201510355175.9）
一种可重构系统的局部重构控制器（ZL201510346718.0）
一种基于可重构技术的二维数据访问动态自适应方法（ZL201410313092.9日）
基于大规模粗粒度嵌入式可重构系统及其处理方法（ZL201410240683.8）
一种粗粒度可重构系统中的配置信息缓存装置及压缩方法（ZL201410177912.6）
一种面向多个粗粒度动态可重构阵列的共享数据缓存结构及控制方法（ZL201410176151.2）
一种基于块匹配的可重构配置信息缓存系统及压缩方法（ZL201410167086.7）
一种粗粒度可重构层次化的阵列寄存器文件结构（ZL201410046664.1）
用于实现可重构系统中配置信息缓存更新的控制器（ZL201310451404.8）
用于实现可重构系统中多任务调度的管理单元和方法（ZL201310338040.2）
用于实现可重构系统中配置信息多发射机制的重构控制器（ZL201310336800.6）
用于实现可重构系统配置信息存储的缓存结构和管理方法（ZL201210538673.3）
基于预先解码分析的数据信息缓存管理方法及系统（ZL201210535995.2）
基于预先解码分析的配置信息缓存管理方法及系统（ZL201210536421.7）

学术兼职

团队介绍

招生情况

诚招有志于开展基于AI的数字集成电路EDA设计方法研究的硕士、博士研究生。

毕业生介绍

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